1. Field of the Invention
The present invention relates to an I/O subsystem and the exclusive control method, data storage method and memory initialization method in the I/O subsystem.
2. Description of the Related Art
A recent large computer system which has increasingly enlarged the scale is generally composed of a plurality of central processing units (CPUs). In such a system, common use of data and communication of data among a plurality of CPUs are necessary. For this purpose, I/O device subsystem including an external storage unit is required to be provided with a multiplicity of host interfaces.
To meet this demand, the I/O subsystem is provided with a multiplicity of input/output controllers (CAs: Channel Adapters) having a plurality of input/output interfaces which are connected to host CPUs. In order to exclusively control the accesses from a plurality of CPUs, the I/O subsystem is provided with an exclusive control manager (RM: Resource Manager) having an exclusive control table.
FIG. 1 shows the structure of a semiconductor disk apparatus as such an I/O subsystem. In FIG. 1, the reference numerals 1a, 1b each represent a CPU, 2 a semiconductor disk controller, and 3 a semiconductor disk having a plurality of semiconductor memory modules 3a, 3b, 3c, . . . The semiconductor disk apparatus has the same structure (command code, data transfer method, etc.) as that of a magnetic disk apparatus except that the magnetic disk as the recording medium is replaced by a semiconductor memory. Therefore, the interface between the CPU 1a (1b) and the semiconductor disk controller 2 is completely the same as the interface between the CPU 1a (1b) and a magnetic disk controller. This semiconductor disk apparatus is advantageous in that instant access is possible because the movement of the head, which is necessary in a magnetic disk, is not necessary, and in that the software resources between the CPU and the magnetic disk controller are usable as they are.
In the semiconductor disk controller 2, the reference numerals 2a and 2b each represent a channel adapter CA having a single or a plurality of interfaces (host interfaces) to and from a host apparatus (CPU), numerals 2c and 2d each a memory interface adapter for controlling the operation of writing/reading data into and from the semiconductor disk 3, numeral 2e represents a resource manager RM having an exclusive control table ECT and executing exclusive control for permitting a host interface to use the semiconductor module 3a (3b or 3c) when another host interface is not using it, while prohibiting the use when another host interface is using it. Exclusive control is executed in each semiconductor memory module.
Two physical interfaces (physical ports) 2a.sub.0, 2a.sub.1 (2b.sub.0, 2b.sub.1) are provided between the channel adapter 2a (2b) and the CPU 1a (1b). The exclusive control table ECT of the resource manager 2e records whether or not each of the semiconductor memory modules 3a, 3b, 3c (device numbers 0 to 2) is occupied by each combination (path) of a channel adapter (channel number) and a physical interface mounted on each channel adapter, as shown in FIG. 2. There are four types of paths, i.e., (00), (01), (10) and (11) in the semiconductor disc controller 2.
In this I/O subsystem, if a command for access to the semiconductor memory module 3b is issued from the CPU 1b to the channel adapter 2b through the physical interface 2b.sub.1, for example, the channel adapter 2b requests the resource manager 2e to permit the use of the semiconductor module 3b. When the resource manager 2e receives the request for use, it judges whether or not the semiconductor memory module 3b is being used through another path by reference to the exclusive control table ECT. If the answer is YES, the resource manager 2e does not permit the channel adapter 2b to use it. On the other hand, if the answer is NO, the resource manager 2e permits the channel adapter 2b to use it, and sets a flag indicating "Occupied" in the field of the semiconductor memory module 3b in correspondence with the path (11). The channel adapter 2b which is permitted to use the semiconductor memory module 3b then receives data from the CPU 1b through the physical interface 2b.sub.1, and writes the data into the semiconductor memory module 3b through the memory interface adapter 2d. When the writing operation is finished, the resource manager 2e changes the flag indicating "Occupied" to a flag indicating "Vacant" in correspondence with the path (11).